US 12,327,586 B2
Bit line pre-charge circuit for power management modes in multi bank SRAM
Sanjeev Kumar Jain, Ottawa (CA); Ruchin Jain, Hsinchu (TW); Arun Achyuthan, Stittsville (CA); and Atul Katoch, Kanata (CA)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Feb. 23, 2024, as Appl. No. 18/585,184.
Application 18/585,184 is a continuation of application No. 18/188,523, filed on Mar. 23, 2023, granted, now 11,935,589.
Application 18/188,523 is a continuation of application No. 17/246,822, filed on May 3, 2021, granted, now 11,626,158, issued on Apr. 11, 2023.
Claims priority of provisional application 63/106,400, filed on Oct. 28, 2020.
Prior Publication US 2024/0242762 A1, Jul. 18, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 11/00 (2006.01); G11C 7/10 (2006.01); G11C 7/12 (2006.01); G11C 11/419 (2006.01)
CPC G11C 11/419 (2013.01) [G11C 7/1093 (2013.01); G11C 7/12 (2013.01); G11C 2207/12 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A bit cell precharge circuit comprising:
wakeup precharge circuitry configured to precharge a first bit line of a first bit cell and a second bit line of the first bit cell, wherein the wakeup precharge circuitry includes:
a wakeup signal path that includes a delay element between the first bit line and the second bit line.