US 12,327,581 B2
Embedded memory IC's with power supply droop circuitry coupled to ferroelectric capacitors
Wilfred Gomes, Portland, OR (US); Abhishek Anil Sharma, Portland, OR (US); and Uygar Avci, Portland, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Dec. 21, 2021, as Appl. No. 17/558,440.
Prior Publication US 2023/0197135 A1, Jun. 22, 2023
Int. Cl. G11C 11/22 (2006.01); H01L 23/48 (2006.01); H01L 23/528 (2006.01); H10B 53/30 (2023.01); H10B 53/40 (2023.01)
CPC G11C 11/2297 (2013.01) [G11C 11/221 (2013.01); H01L 23/481 (2013.01); H01L 23/5286 (2013.01); H10B 53/30 (2023.02); H10B 53/40 (2023.02)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit (IC) die, comprising:
host circuitry comprising first transistors, wherein the host circuitry comprises power supply droop detection circuitry to detect supply voltage droop across power supply rails of the IC die;
an embedded memory array structure coupled to the host circuitry, wherein the embedded memory array structure comprises:
a plurality of first capacitors, each of the first capacitors comprising a first conductor and a second conductor with a ferroelectric material therebetween; and
a plurality of second transistors, wherein a first terminal of each of the second transistors is connected to the first conductor, a second terminal of the second transistors is coupled to one of a plurality of bitlines, and a third terminal of the second transistors is coupled to one of a plurality of wordlines; and
a plurality of second capacitors with conductors coupled to the power supply rails.