US 12,327,580 B2
Register, flop, and latch designs inlcuding ferroelectric and linear dielectrics
Divya Madapusi Srinivas Prasad, Mountain View, CA (US); and Michael Ignatowski, Austin, TX (US)
Assigned to Advanced Micro Devices, Inc., Santa Clara, CA (US)
Filed by Advanced Micro Devices, Inc., Santa Clara, CA (US)
Filed on Jun. 29, 2023, as Appl. No. 18/216,499.
Claims priority of provisional application 63/405,343, filed on Sep. 9, 2022.
Prior Publication US 2024/0087631 A1, Mar. 14, 2024
Int. Cl. G11C 11/22 (2006.01); G11C 19/00 (2006.01)
CPC G11C 11/221 (2013.01) [G11C 19/005 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory circuitry comprising:
a first transmission gate comprising a first transistor connected between a first node and a second node, the first transistor having a gate terminal connected to a first clock node, the first clock node configured to receive a first clock signal;
a first capacitor connected between the second node and a first voltage node, the first capacitor is a ferroelectric capacitor, wherein the first voltage node is configured to receive a second clock signal;
a second transmission gate comprising a second transistor connected between the second node and a third node, the second transistor having a gate terminal connected to the first clock node; and
a second capacitor connected between the third node and a second voltage node.