US 12,327,179 B2
Processor, method of operating the processor, and electronic device including the same
Seung Wook Lee, Suwon-si (KR); Jaeyeon Won, Seoul (KR); Jae Wook Lee, Seoul (KR); and Tae Jun Ham, Seoul (KR)
Assigned to Samsung Electronics Co., Ltd., Suwon-si (KR); and Seoul National University R&DB Foundation, Seoul (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR); and Seoul National University R&DB Foundation, Seoul (KR)
Filed on Jul. 14, 2021, as Appl. No. 17/375,197.
Claims priority of application No. 10-2021-0017469 (KR), filed on Feb. 8, 2021.
Prior Publication US 2022/0253682 A1, Aug. 11, 2022
Int. Cl. G06N 3/063 (2023.01); G06F 5/01 (2006.01); G06F 7/50 (2006.01); G06F 7/523 (2006.01); G06F 7/544 (2006.01); G06F 7/78 (2006.01); G06F 17/16 (2006.01)
CPC G06N 3/063 (2013.01) [G06F 5/01 (2013.01); G06F 7/50 (2013.01); G06F 7/523 (2013.01); G06F 7/5443 (2013.01); G06F 7/78 (2013.01); G06F 17/16 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method of operating a processor, comprising:
arranging weights together in a first input register and arranging activations together in a second input register, the weights and activations each being a smaller number of bits than a minimum operation unit of an operator included in the processor;
performing a multiplication between first values stored in the first input register and second values stored in the second input register, the first values including the weights and the second values including the activations;
storing a result of the multiplication in an output register; and
outputting, from the output register, a value in a preset bit range as a result of a dot product between a first vector including the weights and a second vector including the activations, wherein a most significant bit of one of the weights is arranged at a most significant bit of the first input register and a most significant bit of one of the activations is arranged is arranged at a most significant bit of the second input register.