US 12,327,177 B2
Processing non-power-of-two work unit in neural processor circuit
Christopher L. Mills, Saratoga, CA (US)
Assigned to APPLE INC., Cupertino, CA (US)
Filed by Apple Inc., Cupertino, CA (US)
Filed on Jan. 13, 2021, as Appl. No. 17/148,358.
Prior Publication US 2022/0222509 A1, Jul. 14, 2022
Int. Cl. G06N 3/063 (2023.01); G06F 7/76 (2006.01); G06F 7/78 (2006.01)
CPC G06N 3/063 (2013.01) [G06F 7/764 (2013.01); G06F 7/78 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A neural processor circuit, comprising:
one or more neural engine circuits configured to perform convolution operations on input data corresponding to a neural engine task to generate output data, the one or more neural engine circuits configured to process the input data having a power-of-two (P2) shape; and
a data processor circuit configured to:
fetch source data having a non-power-of-two (NP2) shape, wherein the source data comprises a first plurality of rows each having a first bit width;
reshape the source data to generate reshaped source data with the P2 shape such that the reshaped source data comprises a second plurality of rows that is less than the first plurality of rows, wherein each of the second plurality of rows has a second bit width that is greater than the first bit width; and
send the reshaped source data to the one or more neural engine circuits as the input data.