| CPC G06F 9/5016 (2013.01) [G06F 9/467 (2013.01); G06F 9/5038 (2013.01); G06N 3/04 (2013.01)] | 18 Claims |
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1. A computing system, the system comprising:
a processor comprising at least one core;
a compute processor configured to execute one or more kernels;
a memory coupled to the processor and the compute processor;
wherein the computing system is configured to:
allocate at least one task memory transaction quota to at least a first set of tasks executed on a first core of the processor;
allocate at least one compute processor memory transaction quota for executing the one or more kernels on the compute processor;
execute within a first timing window iteration the at least a first set of tasks and the one or more kernels, wherein the one or more kernels are executed during the first timing window iteration until the at least one compute memory transaction quota for executing the one or more kernels on the compute processor is depleted; and
regulate a rate of memory transaction access by the one or more kernels to the memory when the at least a first set of tasks are executing on the processor;
wherein when execution of one or more tasks of the at least a first set of tasks is completed on a first core prior to an end of the first timing window iteration, the computing system transfers at least a portion of any remaining balance of the at least one task memory transaction quota allocated for the first core to the at least one compute processor memory transaction quota; and
based on completion of the execution of all of the at least the first set of tasks prior to the end of the first timing window, the computing system discontinues regulating the rate of memory transaction access by the one or more kernels, and disabling tracking usage of the compute processor memory transaction quota to the one or more kernels to allow unlimited access by the compute processor to the memory.
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