US 12,327,135 B1
Retimer with host-interactive data logging engine
Ken (Keqin) Han, Fremont, CA (US); Casey Morrison, San Jose, CA (US); Charan Enugala, Newark, CA (US); Pulkit Khandelwal, Cupertino, CA (US); and Vikas Khandelwal, San Jose, CA (US)
Assigned to Astera Labs, Inc., Santa Clara, CA (US)
Filed by Astera Labs, Inc., Santa Clara, CA (US)
Filed on Feb. 26, 2024, as Appl. No. 18/586,821.
Application 18/586,821 is a continuation of application No. 17/240,230, filed on Apr. 26, 2021, granted, now 11,941,436.
Claims priority of provisional application 63/015,456, filed on Apr. 24, 2020.
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 9/54 (2006.01); G06F 9/30 (2018.01); G06F 9/38 (2018.01); G06F 9/48 (2006.01)
CPC G06F 9/4881 (2013.01) [G06F 9/30036 (2013.01); G06F 9/3005 (2013.01); G06F 9/3836 (2013.01); G06F 9/544 (2013.01)] 21 Claims
OG exemplary drawing
 
1. An integrated circuit component comprising:
first and second high-bandwidth signaling interfaces;
a third signaling interface;
a first logging buffer; and
control circuitry to:
forward a stream of symbols received via the first high-bandwidth signaling interface to the second high-bandwidth signaling interface for output from the IC component;
receive a first information-logging command via the third signaling interface; and
store, in the first logging buffer in accordance with the first information-logging command, information corresponding to events detected in connection with the stream of symbols.