US 12,327,117 B2
System, apparatus and methods for performant read and write of processor state information responsive to list instructions
Kameswar Subramaniam, Austin, TX (US); Jason W. Brandt, Austin, TX (US); H. Peter Anvin, San Jose, CA (US); Christopher M. Russell, Austin, TX (US); and Gilbert Neiger, Portland, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Jun. 25, 2021, as Appl. No. 17/358,082.
Prior Publication US 2022/0413859 A1, Dec. 29, 2022
Int. Cl. G06F 9/30 (2018.01); G06F 9/455 (2018.01); G06F 9/48 (2006.01)
CPC G06F 9/30145 (2013.01) [G06F 9/30043 (2013.01); G06F 9/30101 (2013.01); G06F 9/30189 (2013.01); G06F 9/45558 (2013.01); G06F 9/4812 (2013.01); G06F 2009/45591 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A processor comprising:
a front end circuit to fetch and decode a read list instruction, the read list instruction to cause storage, to a memory, of a software-provided list of processor state information;
a first register to store an address of a data table in the memory, wherein the read list instruction comprises a first operand to identify the first register;
a second register to store an address of an address table in the memory to store addresses of a plurality of registers that store the processor state information, wherein the read list instruction comprises a second operand to identify the second register; and
an execution circuit coupled to the front end circuit, wherein the execution circuit, in response to the decoded read list instruction, is to read the processor state information stored in the processor and store each datum of the processor state information into an entry of the data table in the memory.