US 12,327,098 B2
Integrating an embedded controller into a heterogeneous computing platform
Adolfo S. Montero, Pflugerville, TX (US)
Assigned to Dell Products, L.P., Round Rock, TX (US)
Filed by Dell Products, L.P., Round Rock, TX (US)
Filed on Oct. 19, 2022, as Appl. No. 18/047,664.
Prior Publication US 2024/0134619 A1, Apr. 25, 2024
Prior Publication US 2024/0231780 A9, Jul. 11, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 8/41 (2018.01); G06F 9/54 (2006.01)
CPC G06F 8/4434 (2013.01) [G06F 9/54 (2013.01)] 17 Claims
OG exemplary drawing
 
1. An Information Handling System (IHS), comprising:
a heterogeneous computing platform having a Reduced Instruction Set Computer (RISC) processor and a plurality of devices coupled to an interconnect; and
an embedded controller (EC) coupled to the interconnect; wherein the EC comprises:
a processing core integrated into the heterogeneous computing platform; and
a plurality of peripheral devices coupled to the processing core and integrated into the heterogeneous computing platform;
wherein an operating voltage of the heterogeneous computing platform is lower than an operating voltage of an EC-managed device external to the heterogeneous computing platform, wherein the EC-managed device is controlled by a given one of the plurality of peripheral devices, and wherein the IHS further comprises a voltage translator coupled to: (a) a pin of the heterogeneous computing platform that corresponds to the given peripheral device, and (b) the EC-managed device.
 
13. An Information Handling System (IHS), comprising:
a heterogeneous computing platform having a Reduced Instruction Set Computer (RISC) processor and a plurality of devices coupled to an interconnect; and
an embedded controller (EC) coupled to the interconnect;
wherein the EC comprises:
a processing core integrated into the heterogeneous computing platform; and
a plurality of peripheral devices coupled to the processing core and integrated into the heterogeneous computing platform;
another plurality of peripheral devices coupled to the core and external to the heterogeneous computing platform; and
a bus coupled between the processing core and the other plurality of peripheral devices, wherein a voltage used to transmit a signal over the bus is equal to an operating voltage of the heterogeneous computing platform.
 
15. A method, comprising:
providing a run voltage rail to a Reduced Instruction Set Computer (RISC) processor and a plurality of devices within a heterogeneous computing platform; and
providing an always-on voltage rail to an embedded controller (EC) at least partially integrated into the heterogeneous computing platform.