US 12,327,077 B2
Deadlock detection and prevention for routing packet-switched nets in electronic systems
Sreesan Venkatakrishnan, San Jose, CA (US); Nitin Deshmukh, Monroe, WA (US); and Satish B. Sivaswamy, Fremont, CA (US)
Assigned to Xilinx, Inc., San Jose, CA (US)
Filed by Xilinx, Inc., San Jose, CA (US)
Filed on May 4, 2022, as Appl. No. 17/662,037.
Prior Publication US 2023/0359801 A1, Nov. 9, 2023
Int. Cl. G06F 30/394 (2020.01); G06F 30/398 (2020.01); G06F 111/04 (2020.01)
CPC G06F 30/394 (2020.01) [G06F 30/398 (2020.01); G06F 2111/04 (2020.01)] 20 Claims
OG exemplary drawing
 
1. A method, comprising:
generating a graph of a circuit design in which each connected component of the circuit design is represented as a vertex;
generating a routing solution for the circuit design by routing packet-switched nets of the circuit design so that the packet-switched nets of a same connected component do not overlap;
for each routing resource that is shared by packet-switched nets of different connected components, indicating the shared routing resource on the graph by adding an edge;
performing cycle detection on the graph;
for each cycle detected on the graph, breaking the cycle by deleting the edge from the graph and ripping-up at least a portion of the routing solution corresponding to the deleted edge; and
re-routing at least a portion of the circuit design for which the at least a portion of the routing solution was ripped up using an increased cost for a shared routing resource freed from the ripping-up.