US 12,327,075 B2
System and method for clock distribution in a digital circuit
Sarma Vrudhula, Chandler, AZ (US); and Ankit Wagle, Tempe, AZ (US)
Assigned to Arizona Board of Regents on Behalf of Arizona State University, Scottsdale, AZ (US)
Filed by Sarma Vrudhula, Chandler, AZ (US); and Ankit Wagle, Tempe, AZ (US)
Filed on May 1, 2024, as Appl. No. 18/652,787.
Claims priority of provisional application 63/499,973, filed on May 3, 2023.
Prior Publication US 2024/0370617 A1, Nov. 7, 2024
Int. Cl. G06F 30/394 (2020.01); G06F 30/3312 (2020.01)
CPC G06F 30/3312 (2020.01) [G06F 30/394 (2020.01)] 19 Claims
OG exemplary drawing
 
1. A non-transitory computer-readable medium comprising stored instructions, which when executed by a processor, cause the processor to:
modify a synchronous digital logic circuit, the modifying comprising:
replacing a first D flipflop in the circuit with a local-clocking source flipflop; and
connecting a clock output of the local-clocking source flipflop to a clock input of a second D flipflop,
instruct a placing and routing tool that a data path from the first D flipflop of the synchronous digital logic circuit to the local-clocking source flipflop of the synchronous digital logic circuit is a false path, and
place and route the synchronous digital logic circuit,
wherein the replacing and connecting increases an objective function, the objective function being based on the number of high drive strength cells in a logic cone preceding the second D flipflop.