US 12,326,828 B2
Systems and methods for performing link speed switching in a peripheral component interconnect express (PCIe) system
Madhu Yashwanth Boenapalli, Hyderabad (IN); Kaustub Naidu Paila Ram, Hyderabad (IN); Sravani Devineni, Hyderabad (IN); Sai Praneeth Sreeram, Anantapur (IN); Vinod Kumar Kuruma, Jogulamba Gadwal (IN); Rajendra Varma Pusapati, Hyderabad (IN); and Surendra Paravada, Hyderabad (IN)
Assigned to QUALCOMM Incorporated, San Diego, CA (US)
Filed by QUALCOMM INCORPORATED, San Diego, CA (US)
Filed on May 9, 2023, as Appl. No. 18/314,676.
Prior Publication US 2024/0378166 A1, Nov. 14, 2024
Int. Cl. G06F 13/42 (2006.01)
CPC G06F 13/4221 (2013.01) [G06F 2213/0026 (2013.01)] 27 Claims
OG exemplary drawing
 
1. A method for link speed switching in a Peripheral Component Interconnect Express (PCIe) system, the method comprising:
with a pattern checker circuit of a PCIe host processor of the PCIe system, evaluating information over a first predefined period of time relating to a current batch of client requests to identify a modest link speed, wherein the modest link speed corresponds to a bandwidth (BW) associated with a majority of the client requests of the current batch;
determining, in the pattern checker circuit, a number of link speed switching operations that will need to be performed to service the client requests and whether the number exceeds one or more predefined threshold (TH) values;
with a link speed decision circuit of the PCIe system, deciding whether the client requests are to be served at the modest link speed or at respective link speeds associated with the respective client requests and outputting a link speed decision;
deciding, in the link speed decision circuit, that link speed switching is to be performed at the modest link speed if the number exceeds said one or more predefined TH values; and
in a switch of the PCIe system, performing link speed switching based on the link speed decision.