| CPC G06F 13/42 (2013.01) | 19 Claims |
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1. A method for optimizing a signal rise time of a bus, comprising:
constructing an equivalent circuit of a bus link on the basis of a topology of the link, wherein the bus comprises I2C bus, the I2C bus is a bus via which devices in a server product to interact with a control chip being a baseboard management controller;
calculating an equivalent capacitance of the link and a threshold value of pull-up resistance, wherein calculating the equivalent capacitance of the link, comprises:
calculating the equivalent capacitance on the basis of the length of the link and the number of pins of mounted devices in the link;
calculating a time required for a signal of the link to change from a first threshold value to a second threshold value on the basis of the equivalent circuit, the equivalent capacitance, and the threshold value of the pull-up resistance; and
connecting a compensation capacitor in the equivalent circuit and connecting a first transistor in parallel at two ends of the compensation capacitor on the condition that the time required for the signal to change from the first threshold value to the second threshold value does not meet regulations of a bus specification, to optimize the signal rise time, wherein the regulations of the bus specification comprises I2C timing requirement, the optimized signal rise time makes establishment time of the signal of the link meet the I2C timing requirement.
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