| CPC G06F 12/1027 (2013.01) [G06F 12/0292 (2013.01); G06F 12/0891 (2013.01)] | 20 Claims |
|
1. An apparatus comprising:
a context identification circuit configured to:
receive a context identifier assigned to a process being executed by a processor; and
assign, in a given one of a plurality of rename entries, a rename value to the context identifier that has fewer bits than the context identifier; and
a translation lookaside buffer (TLB) circuit coupled to the context identification circuit, wherein the translation lookaside buffer is configured to:
receive a translation request for a particular virtual address that is associated with the process;
cache, in a given TLB entry of the TLB circuit, a translation of the particular virtual address to a corresponding physical address, wherein the given TLB entry is tagged with a portion of the particular virtual address and the rename value; and
in response to a subsequent translation request for the particular virtual address, detect, using both the portion of the particular virtual address and the rename value, a hit on the given TLB entry of the TLB circuit; and
wherein the context identification circuit is further configured to:
in response to the detected hit on the given TLB entry of the TLB circuit, set a used indicator associated with the given rename entry;
after a determination that a threshold number of a plurality of rename values have been assigned, scan the TLB circuit for rename values; and
update used indicators for the plurality of rename entries based on the scan.
|