| CPC G06F 12/1009 (2013.01) [G06F 9/45558 (2013.01); G06F 12/063 (2013.01); G06F 12/1081 (2013.01); G06F 2009/45579 (2013.01); G06F 2009/45583 (2013.01); G06F 2009/45591 (2013.01)] | 20 Claims |
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1. An apparatus comprising:
a plurality of cores to execute instructions;
an input-output (IO) memory management unit (IOMMU) coupled to the plurality of cores, the IOMMU to provide virtualized access to one or more IO devices of a plurality of IO devices by a plurality of guests operating in a virtual execution environment;
one or more base address registers to store one or more base addresses of a corresponding one or more translation structures of a plurality of translation structures associated with a guest of the plurality of guests, the one or more translation structures to be accessed to perform translation operations;
IOMMU virtualization hardware logic to present a virtual IOMMU (vIOMMU) to the guest, the vIOMMU comprising a virtualized representation of the IOMMU, the one or more translation structures associated with the guest to be stored in a private address space accessible to the vIOMMU, the one or more translation structures including one or more context mapping structures to indicate a mapping between the guest and a corresponding one or more IO devices of the plurality of IO devices to which the vIOMMU provides the guest virtualized access, wherein the vIOMMU is to access the one or more translation structures to perform the translation operations, at least one of the translation operations to cause modifications in one or more IOMMU registers;
the IOMMU further comprising:
an IO translation lookaside buffer (IOTLB) to cache one or more translations from the one or more translation operations;
translation circuitry to perform a first sequence of translation operations in response to a first memory access request originating from a first IO device of the plurality of IO devices and comprising first identification information including a process address space identifier (PASID) value, wherein the first sequence of translation operations includes indexing into a first translation structure of the one or more translation structures using at least a portion of the PASID value of the first memory access request; and
the translation circuitry to perform a second sequence of translation operations in response to a second memory access request originating from a second IO device of the plurality of IO devices and comprising second identification information which does not include a PASID value, wherein the second sequence of translation operations includes assigning a PASID value to the second memory access request and using the assigned PASID value for one or more subsequent operations of the second sequence of translation operations to provide a corresponding translation.
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