US 12,326,816 B2
Technologies for offload device fetching of address translations
Saurabh Gayen, Portland, OR (US); Philip R. Lantz, Cornelius, OR (US); Dhananjay A. Joshi, Portland, OR (US); Rupin H. Vakharwala, Hillsboro, OR (US); Rajesh M. Sankaran, Portland, OR (US); Narayan Ranganathan, Bangalore (IN); and Sanjay Kumar, Hillsboro, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Dec. 21, 2020, as Appl. No. 17/129,496.
Prior Publication US 2021/0149815 A1, May 20, 2021
Int. Cl. G06F 12/10 (2016.01); G06F 12/0875 (2016.01); G06F 13/28 (2006.01); G06F 13/40 (2006.01); G06F 13/42 (2006.01)
CPC G06F 12/10 (2013.01) [G06F 12/0875 (2013.01); G06F 13/28 (2013.01); G06F 13/4027 (2013.01); G06F 13/4282 (2013.01); G06F 2212/602 (2013.01); G06F 2212/657 (2013.01); G06F 2213/0026 (2013.01)] 22 Claims
OG exemplary drawing
 
1. An offload device comprising:
an address translation cache (ATC); and
a processing engine implemented at least partially in hardware, wherein the processing engine is to:
receive a translation fetch descriptor from a processor of a compute device to be processed by the processing engine, the translation fetch descriptor comprising an indication of a plurality of virtual memory addresses;
send, in response to receipt of the translation fetch descriptor, a request for a physical memory address corresponding to individual virtual memory addresses of the plurality of virtual memory addresses;
receive, for individual virtual memory addresses of the plurality of virtual memory addresses, a physical memory address;
cache, for individual virtual memory addresses of the plurality of virtual memory addresses, the corresponding physical memory address in the ATC;
send, without reading from or writing to any of the physical addresses corresponding to the plurality of virtual memory addresses, an indication to the processor that the translation fetch descriptor has been processed;
receive a work descriptor from the processor after the indication is sent to the processor that the translation fetch descriptor has been processed, wherein the plurality of virtual memory addresses indicated by the translation fetch descriptor correlates to the work descriptor; and
perform a task identified in the work descriptor by performing direct memory access (DMA) operations to individual physical memory addresses corresponding to individual virtual memory addresses of the plurality of virtual memory addresses by accessing physical memory addresses stored in the ATC and without requesting address translation by an IOMMU during performance of the task.