US 12,326,809 B2
Dynamically allocatable physically addressed metadata storage
David Thomas Chisnall, Cambridge (GB); Nathaniel Wesley Filardo, Cambridge (GB); and Robert McNeill Norton-Wright, Cambridge (GB)
Assigned to Microsoft Technology Licensing, LLC, Redmond, WA (US)
Filed by Microsoft Technology Licensing, LLC, Redmond, WA (US)
Filed on Jul. 26, 2021, as Appl. No. 17/385,765.
Prior Publication US 2023/0029331 A1, Jan. 26, 2023
Int. Cl. G06F 12/02 (2006.01)
CPC G06F 12/0292 (2013.01) [G06F 2212/651 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A computing device comprising:
a processor, the processor having a memory management unit; and
a memory that stores instructions that, when executed by the processor, cause the memory management unit to:
receive a memory access instruction comprising a virtual memory address;
translate the virtual memory address to a physical memory address of the memory, and obtain information associated with the physical memory address, the information including permission information and/or memory type information, the permission information indicating whether permission has been given to store metadata associated with data in the physical memory address, the memory type information indicating whether the metadata is associated with the physical memory address;
determine that the obtained information indicates that the metadata is permitted to be associated with the physical memory address;
based on the determination that the metadata is permitted to be associated with the physical memory address, query a metadata summary table stored in physical memory, the metadata summary table enabling indirection by storing pointers to locations in the physical memory storing metadata;
based on the querying the metadata summary table storing the pointers, determine whether the metadata is compatible with the physical memory address based on the physical memory address being configured to store metadata; and
upon determining that the metadata is incompatible, send a trap to system software of the computing device, the trap triggering dynamic allocation of the physical memory for storing the metadata associated with the physical memory address; and
use a tag controller, the tag controller being part of a cache hierarchy of the computing device, the tag controller being configured to perform cache line evictions and/or cache fills of at least part of the cache hierarchy based on the metadata,
wherein the tag controller is configured to, as part of a cache line eviction, determine that metadata storage is configured for a physical memory address to which the cache line is to be evicted by checking a cache of the tag controller and/or the metadata summary table,
wherein the tag controller is configured to check whether metadata of the cache line being evicted is the same in a threshold number of consecutive chunks, and upon the metadata being the same in the threshold number of consecutive chunks, write the metadata of the cache line being evicted to the metadata summary table, and upon the metadata not being the same in the threshold number of consecutive chunks, write the metadata to the physical memory.