| CPC G06F 12/0246 (2013.01) | 10 Claims |
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1. A flash memory controller, wherein the flash memory controller is configured to access a flash memory module, and the flash memory controller comprises:
a read-only memory (ROM), configured to store a program code;
a microprocessor, configured to execute the program code to control access of the flash memory module;
wherein the microprocessor is configured to perform the steps of:
setting a waiting time in an interrupt coalescing mechanism, and setting a timer, wherein a timeout value of the timer is equal to the waiting time;
receiving multiple commands from a submission queue in a host device, processing the multiple commands to generate multiple command responses respectively, and writing the multiple command responses to a completion queue in the host device;
receiving a submission queue tail and a completion queue head from the host device, wherein the submission queue tail indicates how many commands the host device sends, and the completion queue head indicates how many command responses the host device has read from the completion queue;
when the timer reaches the timeout value, subtracting the completion queue head from the submission queue tail to obtain a queue depth of a command queue inside the host device; and
when the timer reaches the timeout value, sending an interrupt signal to the host device, wherein the interrupt signal is used to trigger the host device to read the multiple command responses from the completion queue.
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