US 12,326,781 B2
Semiconductor device with modified access and associated methods and systems
Aaron Jannusch, Boise, ID (US); Brett K. Dodds, Boise, ID (US); Debra M. Bell, Boise, ID (US); Joshua E. Alzheimer, Boise, ID (US); and Scott E. Smith, Plano, TX (US)
Filed by Lodestar Licensing Group LLC, Evanston, IL (US)
Filed on May 8, 2023, as Appl. No. 18/313,670.
Application 18/313,670 is a continuation of application No. 17/350,099, filed on Jun. 17, 2021, granted, now 11,687,403.
Application 17/350,099 is a continuation of application No. 16/554,913, filed on Aug. 29, 2019, granted, now 11,042,436, issued on Jun. 22, 2021.
Prior Publication US 2024/0078153 A1, Mar. 7, 2024
Int. Cl. G06F 11/10 (2006.01)
CPC G06F 11/1044 (2013.01) [G06F 11/102 (2013.01); G06F 11/1032 (2013.01)] 14 Claims
OG exemplary drawing
 
1. A method, comprising:
enabling a mode of a memory device based on one or more values of a mode register of the memory device, the mode associated with a first burst length of a plurality of burst lengths;
correcting, in accordance with an on-die error-correcting code (ECC) functionality of the memory device, at least one error in first data retrieved from a memory array of the memory device, the first data retrieved based at least in part on a read command;
transmitting, based at least in part on the read command and at a time that is a number of clock cycles after the read command is received, the first data using the first burst length associated with the enabled mode after correcting the at least one error, the number of clock cycles based at least in part on latency information for the memory array;
generating, in accordance with the on-die ECC functionality, a set of ECC bits for second data received via a write command; and
writing, based at least in part on the write command and after generating the set of ECC bits, the second data and the set of ECC bits to the memory array.