US 12,326,775 B2
Self-isolation of power-management integrated circuits of memory modules under fault conditions
Norma Bettine, Chandler, AZ (US); Pavan Kumar, Portland, OR (US); and Justin Tippetts, Hillsboro, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Nov. 30, 2021, as Appl. No. 17/538,052.
Prior Publication US 2023/0168959 A1, Jun. 1, 2023
Int. Cl. G06F 11/00 (2006.01); G06F 11/07 (2006.01); G11C 5/14 (2006.01); G06F 9/4401 (2018.01)
CPC G06F 11/0754 (2013.01) [G06F 11/0706 (2013.01); G06F 11/0772 (2013.01); G11C 5/148 (2013.01); G06F 9/4401 (2013.01)] 21 Claims
OG exemplary drawing
 
1. A power-management integrated circuit (PMIC) comprising:
a PMIC interface configured to be operably engaged with a memory module that is operably engaged with a platform, the memory module comprising a non-volatile memory block having a memory-block power supply controlled by the PMIC;
a critical-fault signal pin, an assertion of which causes the platform to shut down; and
PMIC control logic executable to perform PMIC operations comprising:
determining whether an indicator set of one or more non-volatile critical-fault indicators indicates that at least one prior-cycle critical fault occurred during a prior cycle of operation;
determining whether a current-cycle critical fault occurs during an automatic bootup sequence of the memory-block power supply during a current cycle of operation; and
based on determining that (i) the indicator set indicates that at least one prior-cycle critical fault occurred and (ii) a current-cycle critical fault does occur during the automatic bootup sequence: setting, in the indicator set, a critical-fault indicator corresponding to the occurrence of the current-cycle critical fault; powering down the memory-block power supply; and not asserting the critical-fault signal pin to the platform.