US 12,326,768 B1
Memory calibration in limited power scenario
Robert E. Jeter, Santa Clara, CA (US); Jingkui Zheng, Sunnyvale, CA (US); and Yi Chun Chen, San Jose, CA (US)
Assigned to Apple Inc., Cupertino, CA (US)
Filed by Apple Inc., Cupertino, CA (US)
Filed on Nov. 8, 2022, as Appl. No. 18/053,684.
Claims priority of provisional application 63/376,363, filed on Sep. 20, 2022.
Int. Cl. G06F 3/06 (2006.01); G06F 1/26 (2006.01)
CPC G06F 1/26 (2013.01) [G06F 3/0653 (2013.01); G06F 3/0673 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a portable computing device having a battery and configured to receive power through an external connection, wherein the portable computing device includes:
a charge detection circuit configured to determine a charge state of the battery;
a memory; and
a memory controller coupled to the memory via a memory interface, wherein the memory controller includes a calibration circuit configured to perform one or more calibrations of the memory during a boot-up routine of the portable computing device, and wherein to perform the one or more calibrations, the calibration circuit is further configured to perform calibration operations across a plurality of performance states;
wherein the memory controller is configured to, during the boot-up routine when the portable computing device is receiving power through the external connection and in response to the charge detection circuit determining that the charge state of the battery indicates less than a specified level, modify a manner of performing the calibration operations in one or more of the performance states, where to modify the manner, the memory controller is further configured to cause the calibration circuit to perform calibrations for lower performance states prior to performing calibrations for higher performance states.