US 12,326,752 B2
Synchronization of multiple clock dividers by using lower-frequency clocks and slipping cycles
Robert C. Schell, Chatham, NJ (US)
Assigned to Avago Technologies International Sales Pte. Limited, Singapore (SG)
Filed by Avago Technologies International Sales Pte. Limited, Singapore (SG)
Filed on Apr. 28, 2023, as Appl. No. 18/308,783.
Prior Publication US 2024/0364348 A1, Oct. 31, 2024
Int. Cl. G06F 1/12 (2006.01)
CPC G06F 1/12 (2013.01) 20 Claims
OG exemplary drawing
 
1. A system for synchronizing a plurality of output clocks, the system comprising:
a plurality of frequency dividers configured to receive a plurality of input clock signals and produce a plurality of output clock signals, wherein each of the plurality of output clock signals are lower in frequency than a corresponding input clock signal; and
a circuit configured to:
compare a first output clock signal of the plurality of output clock signals to a second output clock signal of the plurality of output clock signals to determine whether the first output clock signal is synchronized with the second output clock signal;
generate a slip signal in response to determining that the first output clock signal is not synchronized with the second output clock signal; and
apply the slip signal to the second output clock signal to synchronize the second output clock signal with the first output clock signal.