US 12,326,751 B2
Drift detection in timing signal forwarded from memory controller to memory device
Jun Kim, Los Altos Hills, CA (US); Pak Shing Chau, Saratoga, CA (US); and Wayne S. Richardson, Saratoga, CA (US)
Assigned to Rambus Inc., San Jose, CA (US)
Filed by Rambus Inc., San Jose, CA (US)
Filed on Apr. 15, 2024, as Appl. No. 18/635,817.
Application 18/635,817 is a continuation of application No. 18/206,867, filed on Jun. 7, 2023, granted, now 11,983,031.
Application 18/206,867 is a continuation of application No. 17/830,163, filed on Jun. 1, 2022, granted, now 11,709,525, issued on Jul. 25, 2023.
Application 17/830,163 is a continuation of application No. 17/102,119, filed on Nov. 23, 2020, granted, now 11,378,998, issued on Jul. 5, 2022.
Application 17/102,119 is a continuation of application No. 16/566,287, filed on Sep. 10, 2019, granted, now 10,877,511, issued on Dec. 29, 2020.
Application 16/566,287 is a continuation of application No. 15/391,299, filed on Dec. 27, 2016, granted, now 10,496,126, issued on Dec. 3, 2019.
Application 15/391,299 is a continuation of application No. 14/961,077, filed on Dec. 7, 2015, granted, now 9,568,942, issued on Feb. 14, 2017.
Application 14/961,077 is a continuation of application No. 13/656,498, filed on Oct. 19, 2012, granted, now 9,235,537, issued on Jan. 12, 2016.
Claims priority of provisional application 61/551,717, filed on Oct. 26, 2011.
Prior Publication US 2024/0361799 A1, Oct. 31, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 1/08 (2006.01); G06F 1/10 (2006.01); G06F 13/16 (2006.01); H03L 7/07 (2006.01); H03L 7/081 (2006.01); H03L 7/099 (2006.01); H04L 7/00 (2006.01); H04L 7/10 (2006.01)
CPC G06F 1/08 (2013.01) [G06F 1/10 (2013.01); G06F 13/1673 (2013.01); G06F 13/1689 (2013.01); H03L 7/07 (2013.01); H03L 7/0814 (2013.01); H03L 7/0995 (2013.01); H04L 7/0008 (2013.01); H04L 7/0033 (2013.01); H04L 7/10 (2013.01); Y02D 10/00 (2018.01)] 20 Claims
OG exemplary drawing
 
1. A memory device comprising:
a memory core to store data;
an interface circuit to receive, from a memory controller, a first timing signal having a first frequency, wherein the first timing signal is to be used to time a data transfer operation with the memory core;
a drift detection circuit that mimics a timing delay through a clock distribution circuit in the memory device where the clock distribution circuit uses the first timing signal for the data transfer operation, the drift detection circuit comprising a phase to digital converter to determine a phase delay between a second timing signal that is received from the memory controller and the second timing signal that is delayed by a plurality of different delay elements, and the drift detection circuit to generate a digital code that is indicative of the phase delay; and
a transmitter to output information including the digital code to the memory controller.