US 12,004,432 B2
Phase-change memory
Philippe Boivin, Venelles (FR); Roberto Simola, Trets (FR); and Yohann Moustapha-Rabault, Saint-Egrève (FR)
Assigned to STMicroelectronics (Crolles 2) SAS, Crolles (FR); and STMICROELECTRONICS (ROUSSET) SAS, Rousset (FR)
Filed by STMicroelectronics (Crolles 2) SAS, Crolles (FR); and STMICROELECTRONICS (ROUSSET) SAS, Rousset (FR)
Filed on Oct. 21, 2021, as Appl. No. 17/507,645.
Claims priority of application No. 2011087 (FR), filed on Oct. 29, 2020.
Prior Publication US 2022/0140232 A1, May 5, 2022
Int. Cl. H10N 70/00 (2023.01); H10B 63/00 (2023.01); H10N 70/20 (2023.01)
CPC H10N 70/231 (2023.02) [H10B 63/80 (2023.02); H10N 70/021 (2023.02); H10N 70/063 (2023.02); H10N 70/066 (2023.02); H10N 70/068 (2023.02); H10N 70/882 (2023.02); H10N 70/883 (2023.02)] 22 Claims
OG exemplary drawing
 
1. A device, comprising:
phase-change memory cells, each memory cell of the phase-change memory cells including:
a first element of a conductive material has a first surface opposite a second surface, the first surface contacts a second element of a phase-change material; and
a first insulating layer covers the first and second elements, the second surface of the first element is exposed from the first insulating layer;
a third element of a conductive material, an upper surface of the third element in contact with a lower surface of the second element; and
a second insulating layer surrounds the third element,
wherein the second element includes a vertical face extending from the upper face of the third element, the vertical face being in lateral contact with the first element.