US 12,004,376 B2
Display motherboard, preparation method thereof, display substrate and display device
Linhong Han, Beijing (CN); Yi Zhang, Beijing (CN); Guangzhou Zhao, Beijing (CN); Yiyang Zhang, Beijing (CN); Yuqing Yang, Beijing (CN); Tingliang Liu, Beijing (CN); Pengfei Yu, Beijing (CN); Yang Zhou, Beijing (CN); Qun Ma, Beijing (CN); Xiping Li, Beijing (CN); Shikai Qin, Beijing (CN); Weiyun Huang, Beijing (CN); and Yue Long, Beijing (CN)
Assigned to Chengdu BOE Optoelectronics Technology Co., Ltd., Sichuan (CN); and BOE Technology Group Co., Ltd., Beijing (CN)
Appl. No. 17/414,332
Filed by Chengdu BOE Optoelectronics Technology Co., Ltd., Sichuan (CN); and BOE Technology Group Co., Ltd., Beijing (CN)
PCT Filed Dec. 29, 2020, PCT No. PCT/CN2020/140685
§ 371(c)(1), (2) Date Jun. 16, 2021,
PCT Pub. No. WO2021/169568, PCT Pub. Date Sep. 2, 2021.
Claims priority of application No. 202010123204.X (CN), filed on Feb. 27, 2020.
Prior Publication US 2022/0310722 A1, Sep. 29, 2022
Int. Cl. H10K 59/122 (2023.01); H10K 50/84 (2023.01); H10K 71/00 (2023.01); H10K 59/12 (2023.01)
CPC H10K 59/122 (2023.02) [H10K 50/84 (2023.02); H10K 71/00 (2023.02); H10K 59/1201 (2023.02)] 13 Claims
OG exemplary drawing
 
1. A display motherboard, comprising a plurality of display substrate regions and a cutting region located at a periphery of each of the plurality of display substrate regions; wherein the display motherboard further comprises:
a driving structure layer arranged in each of the plurality of display substrate regions and a marking structure layer arranged in each cutting region, wherein the marking structure layer comprises a cutting mark layer; and
a planarization layer arranged on the driving structure layer and the marking structure layer, and covering the marking structure layer;
wherein the driving structure layer comprises a first source-drain metal layer, and the cutting mark layer is arranged on the same layer as the first source-drain metal layer, and the driving structure layer further comprises: a first insulating layer arranged on a base substrate, an active layer arranged on the first insulating layer, a second insulating layer covering the active layer, a first gate metal layer arranged on the second insulating layer, a third insulating layer covering the first gate metal layer, a second gate metal layer arranged on the third insulating layer, and a fourth insulating layer covering the second gate metal layer; wherein the first source-drain metal layer is arranged on the fourth insulating layer, the marking structure layer further comprises: a first insulating layer, a second insulating layer, a third insulating layer and a fourth insulating layer which are stacked on the base substrate, and the cutting mark layer is arranged on the fourth insulating layer; or
wherein the driving structure layer comprises a second source-drain metal layer, and the cutting mark layer is arranged on the same layer as the second source-drain metal layer, and the driving structure layer further comprises: a first insulating layer arranged on a base substrate, an active layer arranged on the first insulating layer, a second insulating layer covering the active layer, a first gate metal layer arranged on the second insulating layer, a third insulating layer covering the first gate metal layer, a second gate metal layer arranged on the third insulating layer, a fourth insulating layer covering the second gate metal layer, a first source-drain metal layer arranged on the fourth insulating layer, and a fifth insulating layer and a first planarization layer covering the first source-drain metal layer, wherein the second source-drain metal layer is arranged on the first planarization layer; the marking structure layer further comprises a first insulating layer, a second insulating layer, a third insulating layer, a fourth insulating layer, a fifth insulating layer and a first planarization layer which are stacked on the base substrate, and the cutting mark layer is arranged on the first planarization layer.