CPC H10B 61/10 (2023.02) [H10N 50/01 (2023.02); H10N 50/80 (2023.02)] | 20 Claims |
18. A memory device comprising:
first electrically conductive lines laterally extending along a first horizontal direction, laterally spaced apart from each other along a second horizontal direction, and located over a substrate;
a two-dimensional array of memory cells located over the first electrically conductive lines, wherein each of the memory cells comprises a vertical stack including a magnetic tunnel junction pillar structure and a selector-containing pillar structure, and each of the first electrically conductive lines contacts a respective row of memory cells arranged along the first horizontal direction;
discrete resist material portions having a tubular configuration and laterally surrounding a respective one of the memory cells;
second electrically conductive lines contacting top surfaces of a respective subset of the memory cells; and
a dielectric matrix layer laterally surrounding the two-dimensional array of discrete resist material portions.
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