US 12,004,357 B2
Cross-point magnetoresistive random memory array and method of making thereof using self-aligned patterning
Lei Wan, San Jose, CA (US); Jordan Katine, Mountain View, CA (US); Tsai-Wei Wu, San Jose, CA (US); and Chu-Chen Fu, San Ramon, CA (US)
Assigned to SANDISK TECHNOLOGIES LLC, Addison, TX (US)
Filed by SANDISK TECHNOLOGIES LLC, Addison, TX (US)
Filed on Mar. 14, 2022, as Appl. No. 17/654,768.
Application 17/477,958 is a division of application No. 16/666,967, filed on Oct. 29, 2019, granted, now 11,152,425, issued on Oct. 19, 2021.
Application 17/354,541 is a division of application No. 16/460,820, filed on Jul. 2, 2019, granted, now 11,056,534, issued on Jul. 6, 2021.
Application 17/654,768 is a continuation in part of application No. 17/477,958, filed on Sep. 17, 2021, granted, now 11,631,716.
Application 17/654,768 is a continuation in part of application No. 17/590,561, filed on Feb. 1, 2022, granted, now 11,765,911.
Application 17/590,561 is a continuation of application No. 16/401,172, filed on May 2, 2019, granted, now 11,271,035, issued on Mar. 8, 2022.
Application 17/654,768 is a continuation in part of application No. 17/354,541, filed on Jun. 22, 2021, granted, now 11,882,706.
Claims priority of provisional application 62/867,590, filed on Jun. 27, 2019.
Prior Publication US 2022/0199686 A1, Jun. 23, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 11/00 (2006.01); H10B 61/00 (2023.01); H10N 50/01 (2023.01); H10N 50/80 (2023.01)
CPC H10B 61/10 (2023.02) [H10N 50/01 (2023.02); H10N 50/80 (2023.02)] 20 Claims
OG exemplary drawing
 
18. A memory device comprising:
first electrically conductive lines laterally extending along a first horizontal direction, laterally spaced apart from each other along a second horizontal direction, and located over a substrate;
a two-dimensional array of memory cells located over the first electrically conductive lines, wherein each of the memory cells comprises a vertical stack including a magnetic tunnel junction pillar structure and a selector-containing pillar structure, and each of the first electrically conductive lines contacts a respective row of memory cells arranged along the first horizontal direction;
discrete resist material portions having a tubular configuration and laterally surrounding a respective one of the memory cells;
second electrically conductive lines contacting top surfaces of a respective subset of the memory cells; and
a dielectric matrix layer laterally surrounding the two-dimensional array of discrete resist material portions.