CPC H10B 61/10 (2023.02) [H10N 50/01 (2023.02); H10N 50/80 (2023.02)] | 20 Claims |
1. A memory array, comprising:
first electrically conductive lines laterally extending along a first horizontal direction and laterally spaced apart along a second horizontal direction;
rows of selector-magnetic tunnel junction (selector-MTJ) assemblies located on a respective one of the first electrically conductive lines, wherein each of the selector-MTJ assemblies comprises a respective row of magnetic tunnel junction (MTJ) pillar structures and a respective row of selector-containing pillar structures that are arranged along the first horizontal direction, and a lateral spacing between neighboring pairs of selector-containing pillar structures that are laterally spaced apart along the first horizontal direction is less than a lateral spacing between neighboring pairs of selector-containing pillar structures that are laterally spaced apart along the second horizontal direction; and
second electrically conductive lines laterally extending along the second horizontal direction and overlying a respective column of the selector-MTJ assemblies.
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