CPC H10B 43/27 (2023.02) [H10B 41/10 (2023.02); H10B 41/27 (2023.02); H10B 41/35 (2023.02); H10B 43/10 (2023.02); H10B 43/35 (2023.02)] | 9 Claims |
4. A three-dimensional memory device, comprising:
an alternating stack of insulating layers and electrically conductive layers;
a plurality of arrays of memory openings vertically extending through the alternating stack;
a plurality of arrays of memory opening fill structures located in the plurality of arrays of memory openings, wherein each of the memory opening fill structures comprises a respective vertical stack of memory elements, and each array of memory opening fill structures comprises a respective set of rows of memory opening fill structures that are arranged along a first horizontal direction, and the plurality of arrays of memory opening fill structures are laterally spaced apart from each other along a second horizontal direction;
a plurality of dielectric plates laterally surrounding a respective array of memory opening fill structures, wherein each of the plurality of dielectric plates has an outer sidewall that is laterally spaced from a most proximal memory opening fill structure within a respective array of memory opening fill structures by a lateral offset distance; and
drain-select-level isolation structures located between a respective neighboring pair of arrays of memory opening fill structures,
wherein each of the drain-select-level isolation structures comprises a respective pair of laterally undulating lengthwise sidewalls including a respective contiguous set of vertically straight and laterally concave sidewall segments that are adjoined to each other.
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