US 12,004,338 B2
Memory device having a diagonally opposite gate pair per memory cell
Giorgio Servalli, Fara Gera d'Adda (IT); Marcello Mariani, Milan (IT); Antonino Rigano, Cernusco sul Naviglio (IT); and Marcello Calabrese, Monza (IT)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Dec. 21, 2021, as Appl. No. 17/645,348.
Prior Publication US 2023/0200048 A1, Jun. 22, 2023
Int. Cl. H10B 12/00 (2023.01); H01L 25/065 (2023.01)
CPC H10B 12/30 (2023.02) [H01L 25/0655 (2013.01); H10B 12/033 (2023.02); H10B 12/48 (2023.02)] 25 Claims
OG exemplary drawing
 
1. An integrated assembly, comprising:
a pillar that includes an upper source/drain, a middle source/drain, a lower source/drain, an upper channel between the upper source/drain and the middle source/drain, a lower channel between the middle source/drain and the lower source/drain, a left-facing vertical surface facing a first direction, and a right-facing vertical surface facing a second direction that is opposite the first direction;
a first gate proximate to the upper channel, wherein the left-facing vertical surface faces the first gate;
a second gate proximate to the lower channel, wherein the left-facing vertical surface faces the second gate;
a third gate proximate to the upper channel, wherein the right-facing vertical surface faces the third gate;
a fourth gate proximate to the lower channel, wherein the right-facing vertical surface faces the fourth gate;
an electrical contact region that is electrically coupled with the upper source/drain; and
a digit line that is beneath the pillar and that is electrically coupled with the lower source/drain.