US 12,004,305 B2
Wiring board and production method for same
Masaya Toba, Tokyo (JP); Kazuhiko Kurafuchi, Tokyo (JP); Takashi Masuko, Tokyo (JP); Kazuyuki Mitsukura, Tokyo (JP); and Shinichiro Abe, Tokyo (JP)
Assigned to RESONAC CORPORATION, Tokyo (JP)
Appl. No. 17/415,041
Filed by Showa Denko Materials Co., Ltd., Tokyo (JP)
PCT Filed Dec. 19, 2019, PCT No. PCT/JP2019/049935
§ 371(c)(1), (2) Date Jun. 17, 2021,
PCT Pub. No. WO2020/130101, PCT Pub. Date Jun. 25, 2020.
Claims priority of application No. 2018-238340 (JP), filed on Dec. 20, 2018.
Prior Publication US 2022/0071019 A1, Mar. 3, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. B32B 3/00 (2006.01); C23C 18/16 (2006.01); C23C 18/20 (2006.01); C23C 18/32 (2006.01); C23C 18/38 (2006.01); H05K 1/03 (2006.01); H05K 3/18 (2006.01)
CPC H05K 3/181 (2013.01) [C23C 18/1605 (2013.01); C23C 18/165 (2013.01); C23C 18/20 (2013.01); C23C 18/32 (2013.01); C23C 18/38 (2013.01); H05K 1/032 (2013.01); H05K 2201/068 (2013.01)] 13 Claims
OG exemplary drawing
 
1. A method for manufacturing a wiring board, the method comprising, in a following order:
(a) a step of adsorbing an electroless plating catalyst to a first insulating material layer;
(b) a step of forming a metal layer on a surface of the first insulating material layer by electroless plating;
(c) a step of forming a resist having an opening for wiring pattern formation on a surface of the metal layer; and
(d) a step of forming a conductive part in a region, which is the surface of the metal layer and is exposed from the resist, by electrolytic plating, wherein
an arithmetic average roughness Ra of the surface of the first insulating material layer is 100 nm or less, and
a nickel content rate of the metal layer is 0.25 to 20% by mass.