CPC H04W 74/0808 (2013.01) [H04W 16/14 (2013.01); H04W 72/0446 (2013.01); H04W 72/0453 (2013.01); H04W 72/23 (2023.01); H04W 74/0833 (2013.01); H04W 76/27 (2018.02)] | 20 Claims |
6. An apparatus comprising:
one or more processors; and
a non-transitory computer readable storage medium storing instructions for execution by the one or more processors, the instructions cause the apparatus to:
transmit a first message in a random access channel (RACH) resource after a first channel access procedure using a contention window size (CWS), the first message including a random access preamble;
maintain the CWS for an uplink (UL) transmission subsequent to the first message, the UL transmission to be based on receipt of a second message to be received during a message reception time window; and
transmit the UL transmission after a second channel access procedure using the CWS, wherein the first channel access procedure and the second channel access procedure are of a type 1 UL channel access procedure type.
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