CPC H04W 72/04 (2013.01) [H04L 1/1812 (2013.01); H04L 5/0053 (2013.01); H04W 4/06 (2013.01); H04W 72/0466 (2013.01); H04L 12/189 (2013.01)] | 11 Claims |
1. A device comprising:
a processor circuit; and
a memory circuit, wherein the memory circuit is arranged to store instructions for the processor circuit,
wherein the processor circuit is arranged to receive at least one first information from a plurality of second devices,
wherein the processor circuit is arranged to receive a resource allocation message from a managing device,
wherein the resource allocation message defines an allocation of bit positions,
wherein the bit positions are associated with an acknowledgement of the at least one first information,
wherein the processor circuit is arranged to transmit an acknowledgement information in response to a reception of the at least one first information from the plurality of second devices.
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