US 12,003,870 B2
Binning in hybrid pixel structure of image pixels and event vision sensor (EVS) pixels
Pooria Mostafalu, Penfield, NY (US); Frederick T. Brady, Webster, NY (US); Sungin Han, Pittsford, NY (US); and Hongyi Mi, Victor, NY (US)
Assigned to Sony Semiconductor Solutions Corporation, Kanagawa (JP)
Filed by Sony Semiconductor Solutions Corporation, Kanagawa (JP)
Filed on Apr. 15, 2022, as Appl. No. 17/721,801.
Prior Publication US 2023/0336881 A1, Oct. 19, 2023
Int. Cl. H04N 25/46 (2023.01); H01L 29/06 (2006.01); H01L 29/66 (2006.01); H01L 31/10 (2006.01); H04N 25/42 (2023.01); H04N 25/70 (2023.01); H04N 25/77 (2023.01)
CPC H04N 25/46 (2023.01) [H04N 25/42 (2023.01); H04N 25/77 (2023.01)] 20 Claims
OG exemplary drawing
 
1. An imaging sensor comprising:
a pixel array including a plurality of pixel circuits; and
a plurality of binning transistors,
wherein a first portion of the plurality of pixel circuits individually includes two or more intensity photodiodes and a second portion of the plurality of pixel circuits individually includes two or more event vision sensor (EVS) photodiodes that are separate and distinct from the two or more intensity photodiodes, and
wherein the plurality of binning transistors is configured to
bin together the first portion,
bin together the second portion, and
bin together the first portion and bin together the second portion, respectively.