CPC H04L 7/033 (2013.01) [H03L 7/0807 (2013.01); H03L 7/087 (2013.01); H04L 7/0004 (2013.01)] | 2 Claims |
1. A clock recovery circuit for a serializer/deserializer comprising:
a clock detector configured to receive a serial data stream from a remote device over a reverse channel, wherein the serial data stream includes clock reference data, and the clock detector configured to output a clock detect signal in response to detecting the clock reference data in the serial data stream;
a phase lock loop including a detector configured to receive the serial data stream and to operate as a phase/frequency detector, or a phase detector; and
a controller configured to receive the clock detect signal and to selectively enable the detector based on the clock detect signal.
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