US 12,003,610 B1
Retimer with mesochronous intra-lane path controllers
Enrique Musoll, San Jose, CA (US); Casey Morrison, San Jose, CA (US); Ken (Keqin) Han, Fremont, CA (US); Pulkit Khandelwal, Cupertino, CA (US); and Subbarao Arumilli, Cupertino, CA (US)
Assigned to Astera Labs, Inc., Santa Clara, CA (US)
Filed by Astera Labs, Inc., Santa Clara, CA (US)
Filed on Apr. 19, 2022, as Appl. No. 17/724,207.
Application 17/724,207 is a continuation of application No. 17/227,272, filed on Apr. 10, 2021, granted, now 11,424,905.
Application 17/724,207 is a continuation of application No. 17/026,454, filed on Sep. 21, 2020, granted, now 11,327,913.
Application 17/227,272 is a continuation in part of application No. 17/026,454, filed on Sep. 21, 2020, granted, now 11,327,913.
Claims priority of provisional application 63/008,292, filed on Apr. 10, 2020.
Claims priority of provisional application 62/903,054, filed on Sep. 20, 2019.
Int. Cl. H04L 7/04 (2006.01); G06F 13/42 (2006.01); H04L 7/00 (2006.01)
CPC H04L 7/0041 (2013.01) [G06F 13/4291 (2013.01); G06F 2213/0026 (2013.01)] 15 Claims
OG exemplary drawing
 
1. A retimer integrated circuit (IC) comprising:
a first signaling interface to concurrently receive a plurality of symbol streams;
clock recovery circuitry to recover respective clock signals from the plurality of symbol streams;
clock selection circuitry to select a first clock signal from the respective clock signals; and
a second signaling interface to concurrently output, from the retimer IC at times indicated by the first clock signal, two or more symbol streams of the plurality of symbol streams;
wherein the first signaling interface to concurrently receive the plurality of symbol streams concurrently comprises circuitry to receive the symbol streams via respective signaling lanes;
wherein the clock selection circuitry to select the first clock signal from the respective clock signals comprises circuitry to select the first clock signal based at least in part on lane-aggregation information that indicates aggregation of one of more subsets of the plurality of lanes into one or more multi-lane communication channels, respectively.