CPC H04L 47/2441 (2013.01) [H04L 45/48 (2013.01); H04L 45/74 (2013.01); H04L 47/2483 (2013.01); H04L 69/22 (2013.01)] | 20 Claims |
1. A packet processing system comprising a processor and memory, the memory storing thereon computer-readable instructions that, when executed by the processor, cause the system to perform operations comprising:
accessing a packet processing graph comprising classifier nodes arranged as a packet processing graph, the classifier nodes comprising a first classifier node and a second classifier node, the first and second classifier nodes being arranged in a first packet processing path of the packet processing graph;
at the first classifier node of the packet processing graph:
storing node match data indicative of a match corresponding to content from a combination of two packet header field types including a first packet header field type and a second packet header field type different from the first packet header field type;
at the second classifier node of the packet processing graph:
storing node match data indicative of a match corresponding to content from at least one packet header field type comprising possible permutations of values of the first packet header field type;
wherein the first classifier node is arranged to precede the second classifier node in the first packet processing path;
processing, by the first classifier node using the combination of the two packet header field types as a graph data object of the packet processing graph, a packet when the packet matches the match data stored at the first classifier node; and
when the packet does not match the match data stored at the first classifier node, sending the packet to the second classifier node via a no-match output of the first classifier node.
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