CPC H04L 25/03949 (2013.01) [H04L 7/0087 (2013.01); H04L 7/033 (2013.01); H04L 25/03057 (2013.01); H04L 25/03885 (2013.01); H04L 7/0025 (2013.01)] | 20 Claims |
6. An apparatus comprising:
a continuous time linear equalizer (CTLE) configured to receive a data signal comprising a plurality of data patterns over a series of signaling intervals and to filter the data signal to generate a filtered data signal having altered signal trajectories;
a voltage comparator configured to generate a sample of the filtered data signal responsive to a sampling clock and according to a decision threshold associated with a decision feedback equalizer coefficient;
a data pattern detection circuit configured to identify a specific data pattern associated with the sample; and
a selection circuit configured to responsively process the sample as (i) a valid data decision, (ii) a phase error sample to provide to a clock recovery circuit for adjusting the sampling clock, or (iii) an unneeded sample which may be ignored.
|