US 12,003,262 B2
Receiver sampling architecture for increased dynamic range using waveform feedback
Jeffrey D. Schmidt, Marion, IA (US)
Assigned to Rockwell Collins, Inc., Cedar Rapids, IA (US)
Filed by Rockwell Collins, Inc., Cedar Rapids, IA (US)
Filed on Oct. 28, 2022, as Appl. No. 17/976,421.
Prior Publication US 2024/0146347 A1, May 2, 2024
Int. Cl. H04B 1/10 (2006.01)
CPC H04B 1/1027 (2013.01) 14 Claims
OG exemplary drawing
 
1. A receiver sampling system, comprising:
radio frequency (RF) circuitry configured for:
receiving an RF input signal associated with a waveform;
and
producing, via manipulation of the RF input signal, a plurality of N substantially equivalent input spectra, where N is an integer;
a set of N parallel sampling paths communicatively coupled to the RF circuitry, each sampling channel corresponding to an input spectrum and comprising:
a sampling clock associated with a predetermined sampling rate, wherein each sampling channel corresponds to an initial sampling rate;
at least one analog-digital converter (ADC) configured to provide a digital input signal based on the input spectrum, the digital input signal including one or more intermodulation products associated with the initial sampling rate;
at least one resampler configured to convert the digital input signal to a baseband modulated I/Q stream associated with a common sampling rate common to the set of N parallel sampling paths;
at least one demodulator in data communication with the one or more ADCs, the at least one demodulator configured to produce, based on the baseband modulated I/Q stream, a demodulated digital signal;
an evaluation block in data communication with the at least one demodulator and comprising:
a memory configured for storage of the demodulated digital signal;
and
evaluation circuitry configured for evaluation of at least one aspect of the demodulated digital signal according to one or more figures of merit (FOM) associated with the waveform, the at least one aspect associated with the one or more intermodulation products and the evaluation corresponding to a time window of a sequence of time windows, the time window associated with the common sampling rate;
and
a path selection circuit in data communication with the N parallel sampling paths via each evaluation block, the path selection circuit configured to:
select at least one demodulated digital signal based on the N evaluations corresponding to the time window;
and
append the selected demodulated digital signal to a demodulated output stream corresponding to the sequence of time windows.