US 12,003,250 B2
Digital-to-analog converter including current cell array
Kyeongjoon Ko, Yongin-si (KR); Jaehyun Park, Seoul (KR); Junhan Bae, Hwaseong-si (KR); Gyeongseok Song, Hwaseong-si (KR); and Jongjae Ryu, Changwon-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Jun. 10, 2022, as Appl. No. 17/837,752.
Claims priority of application No. 10-2021-0075742 (KR), filed on Jun. 10, 2021; and application No. 10-2021-0123417 (KR), filed on Sep. 15, 2021.
Prior Publication US 2022/0399900 A1, Dec. 15, 2022
Int. Cl. H03M 1/12 (2006.01); H03M 1/68 (2006.01); H03M 1/74 (2006.01); H03M 1/06 (2006.01); H03M 1/66 (2006.01)
CPC H03M 1/682 (2013.01) [H03M 1/687 (2013.01); H03M 1/747 (2013.01); H03M 1/0617 (2013.01); H03M 1/66 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A digital-to-analog converter comprising:
a current cell array comprising a plurality of current cells, each current cell of the plurality of current cells being configured to generate a current of a same magnitude;
a first pattern connecting first current cells, among the plurality of current cells, arranged along a diagonal line of the current cell array;
a second pattern connecting second current cells, among the plurality of current cells, arranged along a first oblique line parallel to the diagonal line; and
a third pattern connecting third current cells, among the plurality of current cells, arranged along a second oblique line parallel to the diagonal line, the third pattern being electrically connected to the second pattern,
wherein the diagonal line is between the first oblique line and the second oblique line and
wherein the second current cells and the third current cells are arranged with no second current cell and third current cell in a same row and with no second current cell and third current cell in a same column.