US 12,003,244 B2
Dynamic configuration of spur cancellation
Helena Deirdre O'Shea, San Jose, CA (US); Dmitry Cherniavsky, San Jose, CA (US); Tim Schoenauer, Bavaria (DE); Ali Moaz, Bayern (DE); Rahmi Hezar, San Francisco, CA (US); and Ram Kanumalli, Linz (AT)
Assigned to APPLE INC., Cupertino, CA (US)
Filed by Apple Inc., Cupertino, CA (US)
Filed on Sep. 8, 2021, as Appl. No. 17/469,272.
Prior Publication US 2023/0072903 A1, Mar. 9, 2023
Int. Cl. H04B 1/10 (2006.01); G06F 1/08 (2006.01); G06F 13/40 (2006.01); H03K 5/1252 (2006.01)
CPC H03K 5/1252 (2013.01) [G06F 1/08 (2013.01); G06F 13/4027 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method of performing spur cancellation at a first integrated circuit (IC), comprising:
determining a local clock frequency of a second IC that operates in a repeating sequence of a first interval and a second interval subsequent to the first interval;
determining a start time at which the second IC starts to operate with one or more first operating frequencies in the first interval;
performing, based on the determined local clock frequency of the second IC, the spur cancellation on a signal of the first IC received from the start time to mitigate or remove spurs from the second IC operating with the one or more first operating frequencies;
determining an update time at which the second IC starts to operate with one or more second operating frequencies in the second interval;
determining a change in the local clock frequency of the second IC; and
updating, based on the changed local clock frequency, the spur cancellation on the signal of the first IC from the update time to mitigate or remove the spurs from the second IC operating with the one or more second operating frequencies.