US 12,003,239 B2
Low-power flip flop circuit
Po-Chia Lai, Fremont, CA (US); Meng-Hung Shen, Zhubei (TW); Chi-Lin Liu, New Taipei (TW); Stefan Rusu, Sunnyvale, CA (US); Yan-Hao Chen, Hsin-Chu (TW); and Jerry Chang-Jui Kao, Taipei (TW)
Assigned to Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu (TW)
Filed on Oct. 28, 2022, as Appl. No. 17/976,187.
Application 17/976,187 is a division of application No. 17/180,379, filed on Feb. 19, 2021, abandoned.
Application 17/180,379 is a division of application No. 16/437,541, filed on Jun. 11, 2019, granted, now 10,931,264.
Application 16/437,541 is a division of application No. 15/485,595, filed on Apr. 12, 2017, granted, now 10,326,430.
Claims priority of provisional application 62/428,443, filed on Nov. 30, 2016.
Prior Publication US 2023/0048735 A1, Feb. 16, 2023
Int. Cl. H03K 3/3562 (2006.01); H03K 3/012 (2006.01); H03K 3/0233 (2006.01); H03K 3/037 (2006.01); H03K 3/289 (2006.01); H03K 3/356 (2006.01)
CPC H03K 3/012 (2013.01) [H03K 3/02332 (2013.01); H03K 3/0372 (2013.01); H03K 3/289 (2013.01); H03K 3/356104 (2013.01); H03K 3/3562 (2013.01); H03K 3/35625 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method to operate a flip-flop circuit, comprising:
receiving a scan-in signal and a data signal;
selectively coupling either the scan-in signal or the data signal to coupled master and slave latches; and
based on a clock signal, selectively activating either the master latch or the slave latch so as to latch either the scan-in signal or the data signal as an output signal of the flip-flop circuit, wherein the master latch circuit comprises a pair of cross-coupled AND-OR-Inverter (AOI) logic gates, and the slave latch circuit comprises a pair of cross-coupled OR-AND-Inverter (OAI) logic gates;
providing a logically inverted clock signal to the master latch circuit and the slave latch circuit, respectively; and
delaying the clock signal to the master latch circuit but not delaying the clock signal to the slave latch circuit.