US 12,003,233 B1
High bandwidth integrated multiplexer and driver stage for transmitter
Varun Kant Tripathi, Bengaluru (IN); and Shourya Kansal, Immadihalli (IN)
Assigned to Synopsys, Inc., Sunnyvale, CA (US)
Filed by Synopsys, Inc., Mountain View, CA (US)
Filed on Oct. 28, 2022, as Appl. No. 18/050,822.
Int. Cl. H04B 1/02 (2006.01); G06F 1/04 (2006.01); H03K 17/687 (2006.01); H03K 17/693 (2006.01); H03K 19/0175 (2006.01); H03K 19/20 (2006.01); H04B 1/04 (2006.01)
CPC H03K 17/6872 (2013.01) [G06F 1/04 (2013.01); H03K 17/693 (2013.01); H03K 19/0175 (2013.01); H03K 19/20 (2013.01); H04B 1/04 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A system comprising:
a clock source configured to generate a set of clock signals that are phase-offset;
serialization circuitry configured to convert input data provided through parallel input streams into a lesser number of parallel output streams, whereto to convert the input data, the serialization circuitry samples the input data using the clock signals;
a pre-driver circuit comprising combinational logic including a first multiplexer, wherein the first multiplexer is configured to generate an output of the pre-driver circuit through combining the converted input data such that the lesser number of parallel output streams is further reduced; and
a driver circuit configured to generate, using the output of the pre-driver circuit, a final output stream corresponding to the input data in serial format, wherein the driver circuit is integrated with a second multiplexer, and wherein the output of the pre-driver circuit operates as both control input and data input to the second multiplexer.