US 12,002,876 B2
Semiconductor device
Shunpei Yamazaki, Tokyo (JP); Kenichi Okazaki, Tochigi (JP); Junichi Koezuka, Tochigi (JP); Tomonori Nakayama, Kanagawa (JP); and Motoki Nakashima, Kanagawa (JP)
Assigned to Semiconductor Energy Laboratory Co., Ltd., (JP)
Filed by Semiconductor Energy Laboratory Co., Ltd., Kanagawa-ken (JP)
Filed on Dec. 20, 2022, as Appl. No. 18/084,912.
Application 18/084,912 is a continuation of application No. 17/330,589, filed on May 26, 2021, granted, now 11,538,928.
Application 17/330,589 is a continuation of application No. 15/215,801, filed on Jul. 21, 2016, granted, now 11,024,725, issued on Jun. 1, 2021.
Claims priority of application No. 2015-146351 (JP), filed on Jul. 24, 2015.
Prior Publication US 2023/0132342 A1, Apr. 27, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 29/66 (2006.01); H01L 27/12 (2006.01); H01L 29/04 (2006.01); H01L 29/24 (2006.01); H01L 29/417 (2006.01); H01L 29/49 (2006.01); H01L 29/786 (2006.01); H01L 29/78 (2006.01)
CPC H01L 29/66969 (2013.01) [H01L 27/1225 (2013.01); H01L 29/045 (2013.01); H01L 29/24 (2013.01); H01L 29/41733 (2013.01); H01L 29/4908 (2013.01); H01L 29/78618 (2013.01); H01L 29/78648 (2013.01); H01L 29/7869 (2013.01); H01L 29/78696 (2013.01); H01L 29/7849 (2013.01); H01L 29/786 (2013.01)] 13 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a conductive film;
a first insulating film over the conductive film;
an oxide semiconductor film over the first insulating film;
a second insulating film over the oxide semiconductor film;
a metal oxide film over the second insulating film;
a gate electrode over the metal oxide film; and
a third insulating film over the gate electrode,
wherein the oxide semiconductor film comprises a channel region overlapping with the gate electrode, a source region in contact with the third insulating film, and a drain region in contact with the third insulating film,
wherein the second insulating film comprises a nitride,
wherein the metal oxide film comprises at least one of In, Zn, Al, Ga, Y, and Sn,
wherein the third insulating film is in contact with a top surface and a side surface of the gate electrode, a side surface of the metal oxide film, a side surface of the second insulating film, and a part of a top surface of the oxide semiconductor film, and
wherein the gate electrode is in contact with the conductive film through an opening in the first insulating film, the second insulating film and the metal oxide film.