US 12,002,862 B2
Inter-level handshake for dense 3D logic integration
Lars Liebmann, Mechanicsville, NY (US); Jeffrey Smith, Clifton Park, NY (US); Daniel Chanemougame, Niskayuna, NY (US); and Paul Gutwin, Williston, VT (US)
Assigned to Tokyo Electron Limited, Tokyo (JP)
Filed by Tokyo Electron Limited, Tokyo (JP)
Filed on May 24, 2021, as Appl. No. 17/328,289.
Claims priority of provisional application 63/121,845, filed on Dec. 4, 2020.
Prior Publication US 2022/0181453 A1, Jun. 9, 2022
Int. Cl. H01L 29/786 (2006.01); H01L 27/06 (2006.01); H01L 27/092 (2006.01); H01L 29/06 (2006.01); H01L 29/417 (2006.01); H01L 29/423 (2006.01); H10B 10/00 (2023.01)
CPC H01L 29/41733 (2013.01) [H01L 27/0688 (2013.01); H01L 27/092 (2013.01); H01L 29/0665 (2013.01); H01L 29/41783 (2013.01); H01L 29/42392 (2013.01); H01L 29/78621 (2013.01); H10B 10/125 (2023.02); H10B 10/18 (2023.02)] 16 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a first device plane over a substrate, the first device plane including a first transistor device having a first source/drain (S/D) region formed in an S/D channel;
a second device plane over the first device plane, the second device plane including a second transistor device having a second gate formed in a gate channel which is adjacent to the S/D channel; and
a first inter-level connection from the first S/D region of the first transistor device to the second gate of the second transistor device, wherein the first inter-level connection includes a lateral offset from the S/D channel to the gate channel, wherein
the first inter-level connection comprises the S/D channel, a horizontal portion that contacts the S/D channel, and a vertical portion that connects the horizontal portion to the second gate, and
the vertical portion extends from the first device plane to the second device plane and corresponds to a vertical distance from the first S/D region to the second gate relative to a surface of the substrate.