US 12,002,831 B2
Semiconductor device
Hajime Yamagishi, Kanagawa (JP); Eiji Sato, Kanagawa (JP); Akira Yamazaki, Kanagawa (JP); Takayuki Sekihara, Kanagawa (JP); Makoto Hayafuchi, Kanagawa (JP); and Syunsuke Ishizaki, Kanagawa (JP)
Assigned to Sony Semiconductor Solutions Corporation, Kanagawa (JP)
Appl. No. 17/266,838
Filed by SONY SEMICONDUCTOR SOLUTIONS CORPORATION, Kanagawa (JP)
PCT Filed Aug. 2, 2019, PCT No. PCT/JP2019/030391
§ 371(c)(1), (2) Date Feb. 8, 2021,
PCT Pub. No. WO2020/044943, PCT Pub. Date Mar. 5, 2020.
Claims priority of application No. 2018-162382 (JP), filed on Aug. 31, 2018.
Prior Publication US 2021/0351219 A1, Nov. 11, 2021
Int. Cl. H01L 27/146 (2006.01); H01L 23/00 (2006.01)
CPC H01L 27/14634 (2013.01) [H01L 24/05 (2013.01); H01L 24/08 (2013.01); H01L 27/14636 (2013.01); H01L 2224/05553 (2013.01); H01L 2224/08146 (2013.01)] 14 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a first semiconductor substrate including a first multilayer wiring layer; and
a second semiconductor substrate including a second multilayer wiring layer, wherein the first semiconductor substrate and the second semiconductor substrate are joined together with the first multilayer wiring layer and the second multilayer wiring layer directly connected to each other to form a plurality of conductors in a proximity of a joining plane of the of the first and second semiconductor substrates, wherein connection holes are formed in either or both of the first multilayer wiring layer and the second multilayer wiring layer, wherein rivets are fitted to the connection holes, and wherein the plurality of conductors are electrified in a direction of the joining plane.