US 12,002,818 B2
Semiconductor device and manufacturing method thereof
Masayuki Sakakura, Tochigi (JP); Yoshiaki Oikawa, Sagamihara (JP); Shunpei Yamazaki, Setagaya (JP); Junichiro Sakata, Atsugi (JP); Masashi Tsubuku, Atsugi (JP); Kengo Akimoto, Atsugi (JP); and Miyuki Hosoba, Isehara (JP)
Assigned to Semiconductor Energy Laboratory Co., Ltd., Atsugi (JP)
Filed by Semiconductor Energy Laboratory Co., Ltd., Atsugi (JP)
Filed on Jun. 29, 2023, as Appl. No. 18/215,987.
Application 18/215,987 is a continuation of application No. 17/105,801, filed on Nov. 27, 2020, granted, now 11,695,019.
Application 17/105,801 is a continuation of application No. 16/672,988, filed on Nov. 4, 2019, granted, now 10,854,640, issued on Dec. 1, 2020.
Application 16/672,988 is a continuation of application No. 15/460,652, filed on Mar. 16, 2017, granted, now 10,629,627, issued on Apr. 21, 2020.
Application 15/460,652 is a continuation of application No. 14/264,301, filed on Apr. 29, 2014, granted, now 9,601,516, issued on Mar. 21, 2017.
Application 14/264,301 is a continuation of application No. 12/871,148, filed on Aug. 30, 2010, granted, now 8,742,422, issued on Jun. 3, 2014.
Claims priority of application No. 2009-204565 (JP), filed on Sep. 4, 2009.
Prior Publication US 2024/0014222 A1, Jan. 11, 2024
Int. Cl. H01L 27/14 (2006.01); G02F 1/1343 (2006.01); G02F 1/1345 (2006.01); G02F 1/1368 (2006.01); H01L 27/12 (2006.01)
CPC H01L 27/124 (2013.01) [G02F 1/134309 (2013.01); G02F 1/13454 (2013.01); G02F 1/1368 (2013.01); H01L 27/1225 (2013.01); H01L 27/1255 (2013.01); G02F 2202/10 (2013.01)] 8 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a pixel portion comprising a first transistor and a capacitor; and
a driver circuit portion comprising a second transistor,
wherein the first transistor comprises:
a first gate electrode layer;
a first oxide semiconductor layer, a region of the first oxide semiconductor layer and the first gate electrode layer overlapping with each other; and
a first source electrode layer and a first drain electrode layer each provided under and in contact with the first oxide semiconductor layer,
wherein the capacitor comprises a first conductive layer and a second conductive layer,
wherein the first conductive layer is a same layer as the first gate electrode layer and comprises a same material as the first gate electrode layer,
wherein the second conductive layer is a same layer as the first source electrode layer and the first drain electrode layer and comprises a same material as the first source electrode layer and the first drain electrode layer,
wherein the second transistor comprises:
a second gate electrode layer;
a second oxide semiconductor layer provided over the second gate electrode layer;
a third gate electrode layer provided over the second oxide semiconductor layer; and
a second source electrode layer and a second drain electrode layer each being in contact with the second oxide semiconductor layer, and
wherein the second gate electrode layer and the third gate electrode layer overlap with each other with the second oxide semiconductor layer located therebetween.