US 12,002,805 B2
Local vertical interconnects for monolithic stack transistors
Heng Wu, Guilderland, NY (US); Ruilong Xie, Niskayuna, NY (US); Chen Zhang, Guilderland, NY (US); and Eric Miller, Watervliet, NY (US)
Assigned to International Business Machines Corporation, Armonk, NY (US)
Filed by International Business Machines Corporation, Armonk, NY (US)
Filed on Aug. 13, 2021, as Appl. No. 17/445,013.
Prior Publication US 2023/0051674 A1, Feb. 16, 2023
Int. Cl. H01L 27/06 (2006.01); H01L 21/822 (2006.01); H01L 21/8234 (2006.01); H01L 27/088 (2006.01)
CPC H01L 27/0688 (2013.01) [H01L 21/8221 (2013.01); H01L 21/823475 (2013.01); H01L 27/088 (2013.01)] 7 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a lower level transistor including a first source, a first drain, a first interconnect in direct contact with one of the first source and the first drain, and a second interconnect in direct contact with the other of the first source and the first drain;
an upper level transistor including a second source, a second drain, a third interconnect in direct contact with one of the second source and the second drain, and a fourth interconnect in direct contact with the other of the second source and the second drain;
a dielectric layer arranged between the lower level transistor and the upper level transistor, the dielectric layer including a recess extending to the second interconnect; and
a dielectric cap formed in the recess and arranged in direct contact with the second interconnect,
wherein the first interconnect and the second interconnect are arranged between the lower level transistor and the upper level transistor.