US 12,002,784 B2
Semiconductor package
Yun Seok Choi, Hwaseong-si (KR)
Assigned to Samsung Electronics Co., Ltd., (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Nov. 8, 2022, as Appl. No. 17/983,018.
Application 17/983,018 is a continuation of application No. 17/021,112, filed on Sep. 15, 2020, granted, now 11,515,290.
Claims priority of application No. 10-2020-0025383 (KR), filed on Feb. 28, 2020.
Prior Publication US 2023/0055812 A1, Feb. 23, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 25/065 (2023.01); H01L 23/31 (2006.01); H01L 23/367 (2006.01); H01L 23/48 (2006.01); H01L 23/538 (2006.01)
CPC H01L 25/0652 (2013.01) [H01L 23/3128 (2013.01); H01L 23/3135 (2013.01); H01L 23/367 (2013.01); H01L 23/481 (2013.01); H01L 23/5383 (2013.01); H01L 23/5385 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A semiconductor package comprising:
an upper substrate having a first surface and a second surface opposite to each other,
a lower semiconductor chip on the first surface of the upper substrate;
a plurality of conductive pillars on the first surface of the upper substrate and at least one side of the lower semiconductor chip;
a lower mold layer on the first surface of the upper substrate, the lower mold layer filling a space between the lower semiconductor chip and the plurality of conductive pillars;
a plurality of upper semiconductor chips on the second surface of the upper substrate, the plurality of upper semiconductor chips include a first upper semiconductor chip and a second upper semiconductor chip laterally spaced apart from each other in a first direction parallel to the second surface of the upper substrate and electrically connected to the second surface of the upper substrate;
upper bumps between the first upper semiconductor chip and the second surface of the upper substrate and the second upper semiconductor chip and the second surface of the upper substrate; and
upper underfill layers respectively disposed between the first upper semiconductor chip and the second surface of the upper substrate and the second upper semiconductor chip and the second surface of the upper substrate,
wherein the lower semiconductor chip vertically overlaps a portion of the first upper semiconductor chip and a portion of the second upper semiconductor chip in a second direction perpendicular to the second surface of the upper substrate,
wherein the lower semiconductor chip includes lower through-electrodes penetrating therethrough, one of the lower through-electrodes vertically overlaps the portion of the first upper semiconductor chip in the second direction, and another of the lower through-electrodes vertically overlaps the portion of the second upper semiconductor chip in the second direction,
wherein the upper underfill layers are laterally spaced apart from each other in the first direction, and each of the upper underfill layers covers corresponding ones of the upper bumps,
wherein the lower semiconductor chip and the plurality of conductive pillars are electrically connected to the first surface of the upper substrate.