US 12,002,755 B2
Metallization layer and fabrication method
I-Che Lee, Hsinchu (TW); Huai-Ying Huang, Jhonghe (TW); and Ruei-Cheng Shiu, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on May 5, 2021, as Appl. No. 17/308,404.
Claims priority of provisional application 63/142,574, filed on Jan. 28, 2021.
Prior Publication US 2022/0238438 A1, Jul. 28, 2022
Int. Cl. H01L 21/768 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H01L 23/532 (2006.01); H01L 25/18 (2023.01)
CPC H01L 23/5283 (2013.01) [H01L 21/76807 (2013.01); H01L 21/7684 (2013.01); H01L 21/76843 (2013.01); H01L 21/76883 (2013.01); H01L 21/76888 (2013.01); H01L 23/5226 (2013.01); H01L 23/53238 (2013.01); H01L 25/18 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method comprising:
receiving a substrate having a metal structure directly below a dielectric layer;
forming an opening in the dielectric layer to expose the metal structure
providing a gas that induces metal material from the metal structure to migrate into the opening; and
chemical mechanical polishing that planarizes an upper surface of the metal material within the opening, wherein the chemical mechanical polishing exposes a top electrode of a memory cell.