US 12,002,749 B2
Barrier and air-gap scheme for high performance interconnects
Hsin-Yen Huang, New Taipei (TW); Ting-Ya Lo, Hsinchu (TW); Shao-Kuan Lee, Kaohsiung (TW); Chi-Lin Teng, Taichung (TW); Cheng-Chin Lee, Taipei (TW); Shau-Lin Shue, Hsinchu (TW); and Hsiao-Kang Chang, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Aug. 26, 2021, as Appl. No. 17/412,403.
Prior Publication US 2023/0068892 A1, Mar. 2, 2023
Int. Cl. H01L 23/522 (2006.01); H01L 21/768 (2006.01)
CPC H01L 23/5226 (2013.01) [H01L 21/76831 (2013.01); H01L 21/76832 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated chip, comprising:
a semiconductor substrate;
a dielectric layer disposed over the semiconductor substrate;
a pair of metal lines disposed over an upper surface of the dielectric layer and laterally spaced apart from one another by a cavity, wherein the pair of metal lines have bottom surfaces that are co-planar with the upper surface of the dielectric layer, and a bottom extent of the cavity between the pair of metal lines is defined by the upper surface of the dielectric layer; and
a barrier layer structure extending only along nearest neighboring sidewalls of the pair of metal lines such that lateral extents of the cavity are defined by inner sidewalls of the barrier layer structure.